// `include "add_tc_16_16.v"
`default_nettype none

module add_tc_16_16_tb;
parameter	TCLK = 10;
reg [15:0]  a   ;
reg [15:0]  b   ;
wire [16:0]  sum ;
wire [16:0]  sum_ref ;

initial begin
    $dumpfile("./sim/build/add_tc_16_16_tb.vcd");
    $dumpvars(0, add_tc_16_16_tb);
end

initial begin
    a = 16'h6080;
    b = 16'h8001;
    #TCLK;
    repeat(20)
    begin
        a = {$random}%17'h10000;
        b = {$random}%17'h10000;
        # TCLK ;
    end
    #TCLK;
    $finish;
end

add_tc_16_16 u_add_tc_16_16(
    .a   (a   ),
    .b   (b   ),
    .sum (sum )
);
// ref adder16
assign sum_ref = $signed(a)+$signed(b) ;

endmodule
`default_nettype wire